DSP: boot memory¶
JP150PCB 1.4since 26.10.1generatedJan PřibyslavskýThis page does not apply to the product or PCB revision chosen in the header.
The DSP boot memory of PCB 1.4, a 4 MB SPI flash (W25Q32JV) on the DSP's master port. A
multiplexer lets the module reach it while the DSP is held in reset, so every command here
needs SYS:POWER:MODE SLEEP or STANDBY first and answers DSP_ACTIVE otherwise. PCB 1.3
boots its DSP from an I2C EEPROM that SigmaStudio writes directly; there the commands answer
NO_BUS. DSP: boot memory describes the whole procedure; the
bench tool dsp_flash.py and MuraLink implement it with these commands. Error words are
NO_BUS, DSP_ACTIVE, BAD_ARGS, BUSY, CRC_ERROR, VERIFY_ERROR and FAILED.
Commands¶
| Command | Function | Parameter | Answer | Since | Boards |
|---|---|---|---|---|---|
DSP:FLASH:BUS? |
Levels of the boot-memory bus lines while the DSP is in reset | – | DSP:FLASH:BUS:<sclk>,<mosi>,<miso>,<cs> |
26.10.1 | 1.4 |
DSP:FLASH:ID? |
Identification and status of the boot memory | – | DSP:FLASH:ID:<jedec>,<sr1> |
26.10.1 | 1.4 |
DSP:FLASH:READ? |
Read 1 to 32 bytes | <address>,<length> |
DSP:FLASH:READ:<hex> |
26.10.1 | 1.4 |
DSP:FLASH:ERASE |
Erase 4 KB sectors, at most 64 KB per call | <address>,<length> |
DSP:FLASH:ERASE:OK |
26.10.1 | 1.4 |
DSP:FLASH:WRITE |
Program 1 to 32 bytes, CRC-checked and read back | <address>,"<hex>",<crc32> |
DSP:FLASH:WRITE:OK |
26.10.1 | 1.4 |
DSP:FLASH:CRC? |
CRC-32 of a range, at most 1 MB per call | <address>,<length> |
DSP:FLASH:CRC:<crc32> |
26.10.1 | 1.4 |
Since is the release the command appeared in; 26.6.2 is the oldest release documented here, so a command marked 26.6.2 may be older.
DSP:FLASH:BUS?¶
A diagnostic that checks that the DSP releases the bus in reset. Each field is the level of
the line with the module's internal pull-up, then with its pull-down: 10 means the line
follows the pulls and nothing drives it. A released bus reads 10,10,10,11 (chip select keeps
its own pull-up).
DSP:FLASH:ID?¶
The JEDEC identification (manufacturer, type, capacity) and status register 1 of the flash, in
hex. The W25Q32JV of PCB 1.4 reads EF4016.
DSP:FLASH:READ?¶
Two capital hex digits per byte. An address or length past the end of the 4 MB flash, or a bad
parameter, is an SCPI error without an answer, unlike the error words of the other commands.
Erased flash reads FF.
DSP:FLASH:ERASE¶
Both values are multiples of 4096; up to 64 KB per call, which takes up to about 8 s.
DSP:FLASH:WRITE¶
Programs the quoted hex bytes into erased flash without crossing a 256-byte page. crc32 is
the CRC-32 of those bytes as a decimal number (zlib's crc32); a mismatch answers CRC_ERROR
before anything is programmed. The bytes are read back after programming (VERIFY_ERROR).
DSP:FLASH:CRC?¶
Eight hex digits, for the host to compare with the CRC-32 of the image it wrote. About 15 us
per byte (1 MB in about 16 s), so allow a long timeout. A whole ADAU1452 image (at most about
200 KB) fits in one call; more than 1 MB answers BAD_ARGS.
Changes¶
- 26.10.1: added
DSP:FLASH:BUS?,DSP:FLASH:ID?,DSP:FLASH:READ?,DSP:FLASH:ERASE,DSP:FLASH:WRITE,DSP:FLASH:CRC?.